1. Field of the Invention
The present invention is related to a method for manufacturing an isolation structure and more particularly to a method for manufacturing a shallow trench isolation (STI) structure.
2. Description of Related Art
With the improvement of semiconductor technology, the size of the semiconductor component is continuously decreased even to the sub-micron. Meanwhile, components further shrink to more minute sizes. Accordingly, the isolation between components becomes a very important issue since the isolation can effectively prevent adjacent components from being short circuited.
In order to prevent adjacent components from being short-circuited, generally an isolation layer is added between components. The more widely-applied technique is a local oxidation of silicon (LOCOS) process. However, the LOCOS process has some disadvantages such as the problems resulted from the stress, or the bird's beak formed around the isolation structure. Nowadays, the most popular method used in the industry is a shallow trench isolation (STI) manufacturing process.
FIGS. 1A through 1C are cross-sectional views illustrating a conventional manufacturing process of an STI structure. Initially, as shown in FIG. 1A, a substrate 100 is provided. Then, a patterned pad layer 102 and a patterned mask layer 104 are successively formed in order on the substrate 100. Thereafter, an etching process is implemented to form trenches 106 in the substrate 100 by using the patterned pad layer 102 and the patterned mask layer 104 as a mask.
Then, referring to FIG. 1B, an insulation material layer (not shown) is formed on the substrate 100 and fills up the trenches 106. After that, a chemical mechanical polishing process is implemented by using the patterned mask layer 104 as a polishing stop layer to planarize the insulation material layer. As a result, an insulation layer 108 is formed in the trenches 106. Then, a wet etching process is implemented to remove the residual insulation material layer on the patterned mask layer 104. While the wet etching process is being implemented, a portion of the insulation layer 108 in the trenches 106 may also be simultaneously removed.
Continually, referring to FIG. 1C, the patterned mask layer 104 is initially removed, and then the patterned pad layer 102 is removed by the wet etching process so as to accomplish manufacturing the STI structure.
However, while the patterned pad layer 102 is being removed, the STI structure (the insulation layer 108) underneath the surface of the substrate 100 may be etched by the etchant used in the wet etching process. As a result, divots are formed at the corner regions 110 of the insulation layer 108, which affects the follow-up manufacturing process. For example, since a polysilicon layer is initially formed on the substrate and the etching process is then implemented during the process for manufacturing a gate, the polysilicon layer usually remains in the divots at the corner regions 110 of the insulation layer 108 when the divots exists thereat, which may cause a short circuit in the subsequently formed components.
In addition, the divots are formed not only while removing the patterned pad layer 102, but usually formed while removing the patterned mask layer 104.